00390nam a2200121Ia 4500008004100000082001200041100005500053245009100108563001200199652000900211700002800220852002000248141108s9999    xx            000 0 und d  a621.392  a"SAKTI KUMAR S P, VIGNESH R,AND VIJAY CORNELIUS J"  aVERILOG DESIGN AND SYNTHESIS OF 64-BIT RISC PROCESSOR FOR IMPLEMENTATION  OVER AN FPGA  aWRAPPER  aVHDL  f20055SELFaVELMATHI  G  aCENTRAL LIBRARY