00402nam a2200109Ia 4500008004100000100004600041245011800087563000900205652002000214700003800234852002000272141108s9999    xx            000 0 und d  a"PREETHI K ., LOGANAYAKI D AND PREETHA C"  aCHIP AREA MINIMIZATION USING INTERCONNECT AREA PREDICTION AND SIMULATED ANNEALING AND SUBSEQUENT POWER PREDICTION  aSOFT  aMICROPROCESSORS  f2009aVENKATAVARA PRASADbCSE 959  aCENTRAL LIBRARY