00480nam a2200157Ia 4500008004100000020000900041082000900050100007900059245008200138520000900220563001200229650000900241652000900250700004300259852002000302141108s9999    xx            000 0 und d  aNULL  aNULL  a"ASHWIN CHITTOOR , DAVID SUKUMAR Y , KAMESH L AND SURENDHAR YADAV YELSANI"  aDESIGN AND SIMULATION OF PROGRAMMABLE INTERVAL TIMER IC USING THE VERILOG HDL  aNULL  aWRAPPER  aNULL  aVHDL  fNULL5SSNCEaMr.K NARAYANANg-bEEE 22  aCENTRAL LIBRARY