TY  - BOOK
AU  - KARTHICK B AND VIGNESH V
AU  - Mr.R LEO
TI  - DESIGN AND SIMULATION OF IBM CETRONICS PARALLEL PORT USING VERILOG HDL AND PARTIAL IMPLEMENTATION OF THE HARDWARE USING PAL CHIP
SN  - NULL
U1  - NULL 
KW  - NULL
N2  - NULL
ER  -