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href="/cgi-bin/koha/opac-search.pl?q=ccl=au%3A%22VELMATHI%20G%22&#38;sort_by=relevance&#38;format=opensearchdescription" /> <opensearch:Query role="request" searchTerms="q%3Dccl%3Dau%253A%2522VELMATHI%2520G%2522" startPage="" /> <item> <title> VERILOG SIMULATION OF CHARACTER RECOGNITION IN NEURAL NETWORK </title> <dc:identifier>ISBN:</dc:identifier> <!-- prettier-ignore-start --> <link>/cgi-bin/koha/opac-detail.pl?biblionumber=61677</link> <!-- prettier-ignore-end --> <description> <![CDATA[ <p> By &quot;ARAVINDHAN K N, CHANDRASEKAR S AND JAYAMOHAN J&quot;.<br /> </p> ]]> <![CDATA[ <p> <a href="/cgi-bin/koha/opac-reserve.pl?biblionumber=61677">Place hold on <em>VERILOG SIMULATION OF CHARACTER RECOGNITION IN NEURAL NETWORK</em></a> </p> ]]> </description> <guid>/cgi-bin/koha/opac-detail.pl?biblionumber=61677</guid> </item> <item> <title> NONLINEAR PULSE PROPAGATION THROUGH AN OPTICAL FIBER </title> <dc:identifier>ISBN:</dc:identifier> <!-- prettier-ignore-start --> <link>/cgi-bin/koha/opac-detail.pl?biblionumber=61734</link> <!-- prettier-ignore-end --> <description> <![CDATA[ <p> By &quot;KANNAN S , MESHAK V AND SUBRAMANIBHARATHI K R&quot;.<br /> </p> ]]> <![CDATA[ <p> <a href="/cgi-bin/koha/opac-reserve.pl?biblionumber=61734">Place hold on <em>NONLINEAR PULSE PROPAGATION THROUGH AN OPTICAL FIBER</em></a> </p> ]]> </description> <guid>/cgi-bin/koha/opac-detail.pl?biblionumber=61734</guid> </item> <item> <title> WEB ENABLED DATA ACQUISTION AND CONTROL </title> <dc:identifier>ISBN:</dc:identifier> <!-- prettier-ignore-start --> <link>/cgi-bin/koha/opac-detail.pl?biblionumber=61750</link> <!-- prettier-ignore-end --> <description> <![CDATA[ <p> By JOHN SOLOMON PREM KUMAR L AND GOPINATH V.<br /> </p> ]]> <![CDATA[ <p> <a href="/cgi-bin/koha/opac-reserve.pl?biblionumber=61750">Place hold on <em>WEB ENABLED DATA ACQUISTION AND CONTROL</em></a> </p> ]]> </description> <guid>/cgi-bin/koha/opac-detail.pl?biblionumber=61750</guid> </item> <item> <title> VERILOG DESIGN AND SYNTHESIS OF 64-BIT RISC PROCESSOR FOR IMPLEMENTATION OVER AN FPGA </title> <dc:identifier>ISBN:</dc:identifier> <!-- prettier-ignore-start --> <link>/cgi-bin/koha/opac-detail.pl?biblionumber=61752</link> <!-- prettier-ignore-end --> <description> <![CDATA[ <p> By &quot;SAKTI KUMAR S P, VIGNESH R,AND VIJAY CORNELIUS J&quot;.<br /> </p> ]]> <![CDATA[ <p> <a href="/cgi-bin/koha/opac-reserve.pl?biblionumber=61752">Place hold on <em>VERILOG DESIGN AND SYNTHESIS OF 64-BIT RISC PROCESSOR FOR IMPLEMENTATION OVER AN FPGA</em></a> </p> ]]> </description> <guid>/cgi-bin/koha/opac-detail.pl?biblionumber=61752</guid> </item> <item> <title> DESIGN OF HIGH SPEED HARDWARE FOR FRAGMENTATION CHECKSUM COMPUTATION AND CRC COMPUTATION IN A NETWORK PROCESSOR </title> <dc:identifier>ISBN:</dc:identifier> <!-- prettier-ignore-start --> <link>/cgi-bin/koha/opac-detail.pl?biblionumber=61770</link> <!-- prettier-ignore-end --> <description> <![CDATA[ <p> By ANIRUDDHA N UDIPI.<br /> </p> ]]> <![CDATA[ <p> <a href="/cgi-bin/koha/opac-reserve.pl?biblionumber=61770">Place hold on <em>DESIGN OF HIGH SPEED HARDWARE FOR FRAGMENTATION CHECKSUM COMPUTATION AND CRC COMPUTATION IN A NETWORK PROCESSOR</em></a> </p> ]]> </description> <guid>/cgi-bin/koha/opac-detail.pl?biblionumber=61770</guid> </item> <item> <title> QUALITY BASED ROUTING PROTOCOL FOR OPTICAL NETWORKS </title> <dc:identifier>ISBN:</dc:identifier> <!-- prettier-ignore-start --> <link>/cgi-bin/koha/opac-detail.pl?biblionumber=61853</link> <!-- prettier-ignore-end --> <description> <![CDATA[ <p> By &quot;ADITH KUMAR S, KARTHIK R AND PRAVEEN KUMAR A&quot;.<br /> </p> ]]> <![CDATA[ <p> <a href="/cgi-bin/koha/opac-reserve.pl?biblionumber=61853">Place hold on <em>QUALITY BASED ROUTING PROTOCOL FOR OPTICAL NETWORKS</em></a> </p> ]]> </description> <guid>/cgi-bin/koha/opac-detail.pl?biblionumber=61853</guid> </item> <item> <title> LOW POWER FPGA ARCHITECTURE </title> <dc:identifier>ISBN:</dc:identifier> <!-- prettier-ignore-start --> <link>/cgi-bin/koha/opac-detail.pl?biblionumber=62182</link> <!-- prettier-ignore-end --> <description> <![CDATA[ <p> By &quot;MRIGANK SHARMA, MUKUNDAN S AND MYTHREYA J L&quot;.<br /> </p> ]]> <![CDATA[ <p> <a href="/cgi-bin/koha/opac-reserve.pl?biblionumber=62182">Place hold on <em>LOW POWER FPGA ARCHITECTURE</em></a> </p> ]]> </description> <guid>/cgi-bin/koha/opac-detail.pl?biblionumber=62182</guid> </item> <item> <title> MICROCONTROLLER BASED POLLUTION MONITORING SYSTEM </title> <dc:identifier>ISBN:NULL</dc:identifier> <!-- prettier-ignore-start --> <link>/cgi-bin/koha/opac-detail.pl?biblionumber=62395</link> <!-- prettier-ignore-end --> <description> <![CDATA[ <p> By SATHYA VENKATESH &amp; SRI SATHYA PRIYA.<br /> NULL </p> ]]> <![CDATA[ <p> <a href="/cgi-bin/koha/opac-reserve.pl?biblionumber=62395">Place hold on <em>MICROCONTROLLER BASED POLLUTION MONITORING SYSTEM</em></a> </p> ]]> </description> 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