| 000 | 00469nam a2200145Ia 4500 | ||
|---|---|---|---|
| 008 | 141108s9999 xx 000 0 und d | ||
| 100 | _a"PREETHI K ., LOGANAYAKI D AND PREETHA C" | ||
| 245 | _aCHIP AREA MINIMIZATION USING INTERCONNECT AREA PREDICTION AND SIMULATED ANNEALING AND SUBSEQUENT POWER PREDICTION | ||
| 563 | _aSOFT | ||
| 590 | _aUG | ||
| 652 | _aMICROPROCESSORS | ||
| 700 |
_f2009 _aVENKATAVARA PRASAD _bCSE 959 |
||
| 852 | _aCENTRAL LIBRARY | ||
| 942 | _cPR | ||
| 999 |
_c62041 _d62041 |
||