000 00480nam a2200157Ia 4500
008 141108s9999 xx 000 0 und d
082 _a621.395
100 _a"ANTO DOLPHIN JOSE J M, INDER KUMERASON AND LOGANATHAN R"
245 _aSIMULATION OF ASYNCHRONOUS DATAPATH AND IMPLEMENTATION OF HDLC PROTOCOL USING VERILOG HDL
563 _aWRAPPER
590 _aUG
652 _aVLSI
700 _f2005
_5SELF
_aKANCHANA BHAASKARAN V S
852 _aCENTRAL LIBRARY
942 _cPR
999 _c62452
_d62452