SIMULATION OF ASYNCHRONOUS DATAPATH AND IMPLEMENTATION OF HDLC PROTOCOL USING VERILOG HDL

"ANTO DOLPHIN JOSE J M, INDER KUMERASON AND LOGANATHAN R"

SIMULATION OF ASYNCHRONOUS DATAPATH AND IMPLEMENTATION OF HDLC PROTOCOL USING VERILOG HDL

WRAPPER

Dewey Class. No.: 621.395

SIMULATION OF ASYNCHRONOUS DATAPATH AND IMPLEMENTATION OF HDLC PROTOCOL USING VERILOG HDL

APA

"ANTO DOLPHIN JOSE J M I. K. A. L. R., KANCHANA BHAASKARAN V S, .SIMULATION OF ASYNCHRONOUS DATAPATH AND IMPLEMENTATION OF HDLC PROTOCOL USING VERILOG HDL. : .

Chicago

"ANTO DOLPHIN JOSE J M INDER KUMERASON AND LOGANATHAN R", KANCHANA BHAASKARAN V S, .SIMULATION OF ASYNCHRONOUS DATAPATH AND IMPLEMENTATION OF HDLC PROTOCOL USING VERILOG HDL. : .

Harvard

"ANTO DOLPHIN JOSE J M I. K. A. L. R., KANCHANA BHAASKARAN V S, .SIMULATION OF ASYNCHRONOUS DATAPATH AND IMPLEMENTATION OF HDLC PROTOCOL USING VERILOG HDL. : .

MLA

"ANTO DOLPHIN JOSE J M INDER KUMERASON AND LOGANATHAN R", KANCHANA BHAASKARAN V S, .: . .

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