APA
"SAKTI KUMAR S P V. R. V. C. J., VELMATHI G, .VERILOG DESIGN AND SYNTHESIS OF 64-BIT RISC PROCESSOR FOR IMPLEMENTATION OVER AN FPGA. : .
Chicago
"SAKTI KUMAR S P VIGNESH R,AND VIJAY CORNELIUS J", VELMATHI G, .VERILOG DESIGN AND SYNTHESIS OF 64-BIT RISC PROCESSOR FOR IMPLEMENTATION OVER AN FPGA. : .
Harvard
"SAKTI KUMAR S P V. R. V. C. J., VELMATHI G, .VERILOG DESIGN AND SYNTHESIS OF 64-BIT RISC PROCESSOR FOR IMPLEMENTATION OVER AN FPGA. : .
MLA
"SAKTI KUMAR S P VIGNESH R,AND VIJAY CORNELIUS J", VELMATHI G, .: . .
