DESIGN AND SIMULATION OF IBM CETRONICS PARALLEL PORT USING VERILOG HDL AND PARTIAL IMPLEMENTATION OF THE HARDWARE USING PAL CHIP (Record no. 62496)
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| 000 -LEADER | |
|---|---|
| fixed length control field | 00571nam a2200193Ia 4500 |
| 020 ## - INTERNATIONAL STANDARD BOOK NUMBER | |
| ISBN | NULL |
| 082 ## - DEWEY DECIMAL CLASSIFICATION NUMBER | |
| Classification number | NULL |
| 100 ## - MAIN ENTRY--AUTHOR NAME | |
| Personal name | KARTHICK B AND VIGNESH V |
| 245 ## - TITLE STATEMENT | |
| Title | DESIGN AND SIMULATION OF IBM CETRONICS PARALLEL PORT USING VERILOG HDL AND PARTIAL IMPLEMENTATION OF THE HARDWARE USING PAL CHIP |
| 520 ## - SUMMARY, ETC. | |
| Summary, etc | NULL |
| 650 ## - SUBJECT ADDED ENTRY--TOPICAL TERM | |
| Topical Term | NULL |
| 652 ## - SUBJECT ADDED ENTRY--REVERSE GEOGRAPHIC (BK MP SE) [OBSOLETE] | |
| Geographic name of place element | VHDL |
| 852 ## - LOCATION/CALL NUMBER | |
| Location | CENTRAL LIBRARY |
| 942 ## - ADDED ENTRY ELEMENTS (KOHA) | |
| Koha item type | Project Report |
| Home library | Current library | Date acquired | Full call number | Accession Number | Koha item type | Department |
|---|---|---|---|---|---|---|
| Central Library - SSNCE | Central Library - SSNCE | 08/11/2014 | NULL | PR90 | Project Report | EEE |