| Item type | Current library | Call number | Status | Notes | Barcode | |
|---|---|---|---|---|---|---|
Books
|
Central Library - SSNCE | 621.397 32 JAC (Browse shelf(Opens below)) | Available | IT | 34878 |
Total holds: 0
Browsing Central Library - SSNCE shelves Close shelf browser (Hides shelf browser)
| 621.397 32 ASH SEMICONDUCTOR MEMORIES: TECHNOLOGY TESTING AND RELIABILITY | 621.397 32 ASH SEMICONDUCTOR MEMORIES: TECHNOLOGY TESTING AND RELIABILITY | 621.397 32 ASH SEMICONDUCTOR MEMORIES: TECHNOLOGY TESTING AND RELIABILITY | 621.397 32 JAC THE MONTE CARLO METHOD FOR SEMICONDUCTOR DEVICE SIMULATION | 621.397 32 KUR MULTI VOLTAGE CMOS CIRCUIT DESIGN | 621.397 32 RAZ DESIGN OF ANALOG CMOS INTEGRATED CIRCUITS | 621.397 32 RAZ DESIGN OF ANALOG CMOS INTEGRATED CIRCUITS |
TBH 04-07-2009 Supplier
There are no comments on this title.
Log in to your account to post a comment.
Text