CHIP AREA MINIMIZATION USING INTERCONNECT AREA PREDICTION AND SIMULATED ANNEALING AND SUBSEQUENT POWER PREDICTION (Record no. 62041)

MARC details
000 -LEADER
fixed length control field 00469nam a2200145Ia 4500
100 ## - MAIN ENTRY--AUTHOR NAME
Personal name "PREETHI K ., LOGANAYAKI D AND PREETHA C"
245 ## - TITLE STATEMENT
Title CHIP AREA MINIMIZATION USING INTERCONNECT AREA PREDICTION AND SIMULATED ANNEALING AND SUBSEQUENT POWER PREDICTION
652 ## - SUBJECT ADDED ENTRY--REVERSE GEOGRAPHIC (BK MP SE) [OBSOLETE]
Geographic name of place element MICROPROCESSORS
852 ## - LOCATION/CALL NUMBER
Location CENTRAL LIBRARY
942 ## - ADDED ENTRY ELEMENTS (KOHA)
Koha item type Project Report
Holdings
Home library Current library Date acquired Accession Number Koha item type Department
Central Library - SSNCE Central Library - SSNCE 08/11/2014 PR959 Project Report CSE
Visitor CountersVisitor Counters

Last Update: 01.07.2026